The present invention relates to electronic component packaging, and more specifically, to a wafer level processing for an electronic component packaging.
Electronic components are packaged in order to interconnect them with other devices. The packaging of the electronic device usually includes contacts for transmitting signals providing power and ground connections between the internal circuitry of the device and external circuitry. Some examples of prior art contacts include wire bonds protruding from the ends of a discrete diode or resistor, or metal caps located on the ends of a fuse. Sophisticated electronic devices such as microprocessors may require several hundred contacts. Those devices are usually produced in a package having multiple pins for mounting to a printed circuit. The electronic component is typically placed in a package, and each contact area on the electronic component is wire bonded to the corresponding pin on the package. Because each wire bond is individually added to the circuit, however, large number of contacts make wire bonding expensive. Additionally, because of the precision required for wire bonding, wire bonding may result in short circuits and similar problems. Furthermore, wire bonds can degrade chip performance because of the length of the wires.
One prior art method of solving the problems of wire bonds is the flip chip.
FIGS. 1A and 1B illustrate a prior art electronic component that is packaged as a flip chip. The flip chip 110 includes an integrated circuit 120 (IC) and solder balls 140 attached to the IC 120. The IC 120 is a conventional integrated circuit, which has contact points, to which solder balls 140 are attached. The flip chip 110 is placed on a substrate 150 which includes a plurality of contact pads. The solder balls 140 of flip chip 110 are reflowed to attach the flip chip 110 to the contact pads on the substrate. In order to prevent solder joint failure caused by coefficient of thermal expansion (CTE) mismatch between substrate 150 and flip chip 110, the area between the solder balls 140 is filled with an underfill 130. The underfill 130 is injected between the IC 120 and the substrate 150. The underfill 130, substrate 150, IC 120 and solder balls 140 form a single unit.
The solder balls 140 act as attachment material that allows the flip chip 110 to be attached to the substrate 150. The silicon of the flip chip 110 and the substrate 150 usually have different CTEs and expand and contract at different rates due to thermal cycling. This lack of compliance causes failures. Underfill 130 generally does not aid compliancy, but constrains the die, solder, and substrate so there will not be failure due to CTE mismatch. The underfill 130 requires extra processing steps, costs, and has other disadvantages.
Most flip chips can not be easily probed with standard testing equipment without causing possible damage to the solder balls. This leads to a chip which requires more expensive equipment for testing.
Furthermore, flip chips 110 generally have no compliancy mechanism to withstand thermal cycles. This lack of compliancy causes failures.
Furthermore, flip chips 110 generally place lead connections directly on the surface of the die. Because there is no compliancy in the flip chips, thermal cycling can cause significant stress on the die surface. Therefore, there should be no active surfaces directly below the bond pads or junction areas to which the solder balls are attached. This leads to a loss of silicon real estate.
Furthermore, in most cases the underfill 130 prevents rework of the die once the underfill 130 is added. The die may be removed, but it is no longer usable, and a new die must be used.
Furthermore, most flip chips 110 use solder balls 140 that are the same size on each die. This does not allow the use of a larger solder ball for power and smaller solder balls for signals in individual dies. Having connective surfaces (solder balls 140) of the same size also prevents the flip chip from providing a large contact area for heat sinks.
One object of the present invention is to provide an integrated passive component which has an integral package manufacturable at a wafer level.
Another object of the present invention is to provide for a circuit package which provides flexibility and compliancy.
Another object of the present invention is to provide an encapsulation of the package in order to provide protect to the circuit.
Another object of the present invention is to provide for the capability for testing a packaged electronic component at the wafer level using standard testing equipment.
A method and apparatus for a packaged passive or active component using wafer level processing is described. A shaped thin film is deposited over a substrate. A first insulating layer is placed over the thin film and substrate. Posts are placed on the substrate. A conductive layer is deposited over the posts, the conductive layer in contact with the thin film. The conductive layer on the top of the posts is for coupling the package to traces on a printed circuit board.
Other objects, features, and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.